Zero Detect-Based Low Power Registers File Access

With the intention of reduce significantly the energy that wastes away when having a read or write access to the register file, since the technique Zero Detect diminishes the transfers of chains of bits for each one of the accesses already mentioned. In this paper is presented an improvement in the reduction of the energy consumption for the register file of a superscalar processor with the technique of Zero Detect, for which the registration is divided in chains of 32, 16, 8 y 4 bit’s (word, integer, byte and nibble). The realized experiments show that it is possible to diminish the consumption of potency up to 50%.